ASICs & Standard Blocks

SCL has been designing and developing ASICs and CCDs for meeting requirements of the Country. Out of the ASICs and CCDs developed by SCL, 4K Linear Imager and Clock Driver have been used in Indian Mini Satellite (IMS) for remote sensing application. SCL has been regularly providing, for over a decade, a set of nine ASICs for control electronics of 3-Phase Electric Locomotive of Indian Railways (IR). SCL will, in future also, continue to provide these nine ASICs to IR for the Locomotive.

SCL has been part of many international collaborations and have provided ASICs for applications therein. Major one is development and delivery of required quantity of Multiplexed Analog Signal Processor (MANAS) ASIC for an International Experiment at CERN-Switzerland. In future, SCL’s participation in such collaborations will continue for development and delivery of ASICs for required applications.

SCL has, in-house designed, over 30 ASICs / Standard Blocks in the last one year generating internal IPs and other circuit blocks focused for meeting requirements of ISRO Centres / Units and other applications. These Standard Blocks include Microcontroller, 14-bit Analog to Digital Converter (ADC), Phase Locked Loop (PLL), Low Voltage Differential Signalling Transmitter/Receiver, Sigma Delta ADC, CMOS Image Sensor, 32KB SRAM, 8-bit Shift Register, 8-bit Binary Counter, Operational Amplifier, Linear Voltage Regulator (LVR), 16-bit Buffer and Transceiver.

Main Features of some of SCL's Standard Blocks

Microcontroller
1.8v operating voltage
Operating frequency of 50 MHz
Sixteen-bit program counter (PC) and data pointer (DPTR)
Two 16-bit timer/counters: T0 & T1
Full duplex serial data receiver/transmitter (UART)
Demultiplexed I/O port structure


 

14 bit Pipelined ADC
Pipeline architecture has inherent sampling latency
Operating voltage for IO pads        : 3.3V
Conversion Rate                                 : 10MSPS
Data Output Coding                           : Straight Binary
No Missing Codes                               : 14 bits Guaranteed
Power Dissipation                              : 350 mW typical

 

Phase Locked Loop
Input Frequency Range 5MHz – 43 MHz
Feedback Loop Divider of 28
Output Frequency Range 140MHz – 1.204GHz
Loop Bandwidth of 1MHz
Charge Pump Linear Range of 0.4V- 2.8V

 

Quad Low Voltage Differential Signal Transmitter/Receiver
3.3V power supply for core and I/O pads
Switching speed 1Gbps
400 Mbps (200 MHz) switching rates
Cold sparing for high reliability and redundancy applications
Compatible with ANSI/TIA/EIA-644 LVDS standard

 

Sigma Delta ADC
16 Bit Resolution
4 Multiplexed Differential Input Channels
PGA from 1 to 128 in Binary Steps
Programmable Output Data Rate upto 640 Hz
SPI Compatible Interface
Offset Calibration and Gain Calibration
Automatic Channel Scanning
Programmable Modulator Sampling Frequency
Over-Range Detection

 

CMOS Image Sensor
64 x 64 pixels
Rolling Integration
Variable Integration Time
Autozeroing (Column Level)
Background Subtraction (Column level)
Black Level Reference
Independent Modular Testing
Test Mode for Measuring

 

32 KB SRAM
Asynchronous 32KB CMOS SRAM
Access time ~16 ns
15-bit Address bus & 8-bit Data bus

 

8 Bit Shift Register
8-Bit Shift Register analogous to 54HC595
Device contains an 8-bit serial-in, parallel-out shift register feeding an 8-bit D-type storage register which is having eight 3- state outputs

 

8 Bit Binary Counter
8-Bit Binary Counter analogous to 54HC590
Device contains an 8-bit binary counter (CCK clk) feeding an 8-bit storage register (RCK clk) having parallel outputs.  Expansion of this 8-bit to multiple bits can be done with cascading facility (RCO & CCKEN)

 

Operational Amplifier
Gain                                          : 105 dB
Unity-Gain Bandwidth (UGB) : 31 MHz
Phase Margin                             : 73 deg
Gain  Margin                               : 13 dB
Power Diss.                                : 13 mW
Settling Time (Rise) 0.05%   : 43 ns
Slew Rate (Rise)                       : 70 V/us
Common Mode Rejection Ratio (CMRR)  : -91 dB
Power Supply Rejection Ratio (PSRR)     : -82 dB
Offset Voltage                           : 8.5 mV
Total eq. Inp noise                   : 145 uV
Total Harmonic Distortion      : -70 dB

 

Voltage Regulator
Down converts I/P supply range of 3.6V - 2.6V to 1.8V
Full load current sourcing capability of 150mA
Junction temperature range of -40 to 125 deg C
Bandgap reference circuit with 5-bit trimming
Short circuit protection circuit
Over temperature protection circuit with hysteresis

 

16 Bit Buffer
Pin compatible with SN54LVTH162244
Output Ports Have Equivalent 22-W Series Resistors, So No External Resistors are Required
Support Mixed-Mode Signal Operation (5-V  Input and Output Voltages with 3.3-V VCC)
Support Unregulated Battery Operation Down to 2.7 V
Typical VOLP (Output Ground Bounce) <0.8 V at VCC =  3.3V,  TA = 25C
Ioff and Power-Up 3-State Support Hot  Insertion
Bus Hold on Data Inputs Eliminates the Need for External  Pullup/Pulldown Resistors
Minimized  High-Speed Switching Noise
ESD Protection Exceeds JESD 22  – 2K-V Human-Body Model (A114-A)

 

16 Bit Transceiver
16-bit (dual-octal) non-inverting 3-state transceiver for low-voltage (3.3-V) operation
Capability to provide a TTL interface to a 5-V system environment
Data transmission from the A to B bus or from B to A bus, depending on the logic level at  the direction-control input
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state
Fully specified for hot-insertion applications using Ioff circuitry and power-up 3-state

 

Many ASICs have been realized at SCL as per the requirements of ISRO/DOS Centres/Units. For further information, kindly send E-mail at vlsi_info@scl.gov.in