VLSI Design activity in SCL is spread over the domains of Analog, Mixed Signal, Digital, Power, Memory, RFCMOS, and Opto-Electronic. Various designs in the form of ASICs / ASSPs / SoCs/ Test Chips have been fabricated, tested, qualified, and delivered to end users. Besides, in-house design activities are pursued for the development and enhancement of products for potential future applications. Designs have been silicon-proven and qualified to space-grade or high reliability levels for induction in space and other strategic programs, as catalogued in the products section.
Key Design Domains
- Power Management
- Data Communication
- Data Converters
- Sensor Signal Conditioning
- Logic Design
- Memory
- RFCMOS
- Opto-Electronics – ROIC
- RadHard By Design
- SoC
Design Implementation Activities
- Feasibility Analysis
- Architecture Defining
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HDL Coding / Schematic Entry / Netlist Entry
- Electrical (Verification / Simulation)
- Synthesis
- DFT & ATPG
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Floorplan / Placement / CTS / Routing
- Full Custom Layout
- Physical Verification (DRC & LVS)
- Physical Parasitic Extraction (PEX)
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Physical STA / Post Layout Simulation
- Electromagnetic (EM) Simulation
- Electromigration & IR drop analysis
- Chip Finishing & GDSII Release
- Design Automation
- Design Flow Establishment
- PDK Support and Delivery
- Standard Cell Library
Memory Cuts & Cell Libraries
| Type | Description |
|---|---|
| Standard Cells | 1.8V- Standard Cell Library (540 cells; 10 Tracks) |
| Standard Cells (RHBD) | 1.8V- Standard Cell Library (56 cells; 30 Tracks) |
| Memory Cuts | SP-SRAM : 4 metal 17 cuts, 6 metal 20 cuts ; DP-SRAM : 4 metal 20 cuts, 6 metal 20 cuts |
| I/O Cells | 1.8V Core / 1.8V I/O ; 3.3V Core / 3.3V I/O ; 5.0V Core / 5.0V I/O ; 1.8V Core / 3.3V I/O ; 1.8V Core / 5.0V I/O |
List of Silicon Proven IPs
- Radiation Hardened (RH) : Standard Library (56 cells)
- Standard SPRAM Cuts(4LM) (17 Cuts)
- Standard SPRAM Cuts(6LM) (20 Cuts)
- Standard DPRAM Cuts(4LM) (20 Cuts)
- Standard DPRAM Cuts(6LM) (20 Cuts)
- LVDS Receiver : 400 Mbps
- LVDS Transmitter : 400 Mbps
- LDO1 : 1.8V/12mA
- LDO2 : 1.8V/5mA
- LDO3 : 1.8V/150mA
- Voltage Reference 1 : 1.25 V
- Voltage Reference 2 : 1.2 V
- CMOS Temperature Sensor 1 : 4mV/°C
- CMOS Temperature Sensor 2 : 11mV/°C
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Temperature Compensated Oscillator : 128 kHz
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Current Feedback Instrumentation Amplifier (CFIA) : Programmable gain up to 32 V/V.
- Power-on-Reset (PoR) : 100ms
- SPI Controller : 10 Mbps
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Microcontroller : 8 bit, 8051 compatible
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RF L Band LNA : Gain 12dB, Noise Figure 3.4dB, P1dB -0.6dBm
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PLL : Integral Clock generation upto 1.2 GHz
EDA Software
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Synopsys
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Cadence
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Siemens
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Keysight
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Cogenda
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Mathworks