VLSI Design

A VLSI Design activity in SCL is spread over the domains of Analog, Mixed Signal, Digital, Memory, RFCMOS and Opto-Electronic. Various designs in form of ASICs / ASSPs / SoCs / Test Chips has been fabricated, tested, qualified and delivered to the end users. In-house technology development activities are also pursued for development of potential future applications and enhancement of present products.Designs have been silicon proven and qualified to space grade / high reliability levels for induction in space and other strategic programs as catalogued in Products section.

 

 

 

 

 

 


VLSI Design Hall

Design Domains

Power Management
Data Communication
Data Converters
Sensor Signal Conditioning
Logic Design
Memory
RFCMOS
ROIC for Imaging
RadHard By Design








Design Implementation Activities

HDL Coding / Schematic Entry / Netlisting Physical Verification (DRC & LVS)
Electrical (Verification / Simulation) Parasitic Extraction
Synthesis STA / Post Layout Simulation
DFT & ATPG Electromagnetic (EM) Simulation
Floorplan / Placement / CTS / Routing Electromigration & IR drop analysis
Full Custom Layout Chip Finishing & GDSII Release



PDK & Cell Library Activities

Cell Library Optimization & Characterization
Type Description
Standard Cells 1.8V- Standard Cell Library
(540 cells; 10 Tracks)
Standard Cells (RHBD) 1.8V- Standard Cell Library
(56 cells; 30 Tracks)
Memory Cuts SP-SRAM : 17 cuts
DP-SRAM : 10 cuts
I/O Cells 1.8V Core / 1.8V I/O &
1.8V Core / 3.3V I/O
Design Automation
Design Flow Establishment
PDK Support and Delivery