VLSI Design

SCL has developed suites implementing full Electronic Design Automation (EDA) Flows for Digital, Mixed Signal and Analog ASIC Design. Wide spectrum industry standard EDA tools viz. Cadence / Synopsys Design tools backed by state of the art hardware and a highly experienced design team is the core strength of SCL.

Key Design Capabilities :

 

 

 

 

 

 


VLSI Design Hall

Domains
References
Power Management
Data Communication
Data Converters
Sensor Interfaces, Amplifiers
Systems on Chip (SoCs)



ASIC / Logic Design Implementations

HDL Code / Gate Level Netlist / Schematic Entry
Key Capabilities of 180 Nanometer Technology at SCL
Gate Density 100K gates / mm
Core Clock 800 MHz
I/O Data Rate 130 MHz @ 40 pF & 20 nH
Bit Cell Size (SRAM) 4.7 μmē /bit (14 Mbit SRAM )
Metal Layers 4 - 6
Power Supply (VDD) 1.8V core CMOS & 3.3V I/O
Gate Delay 27.3 - 29.4 ps/gate
Synthesis / DFT / ATPG / Embedded-Memory
Layout and Physical Verification
   
Cell Library for Logic Design
Cell Library Optimization & Characterization

Handling of Electronic Design Automation (EDA) Tools at Various Steps

Analog / Digital / Mixed Signal Design Flow
Script Writing