Multi-Project-Wafer (MPW)

Semi-Conductor Laboratory (SCL) undertakes regular Multi Project Wafer (MPW) Runs for ASICs / Standard Blocks, designed in-house, for meeting requirements of the Country. SCL offers opportunity to academia to realize circuits designed by students / research scholars / faculty by providing a small part of the Silicon area (subject to availability) on two out of various MPW Runs undertaken every year, typically one each in June and December. Designs for these MPW Runs should be submitted to SCL at least 2 months in advance (typically in April and October respectively). Provision of a part of Silicon area, in future, for other users is under active consideration.

For details, please contact : Group Head - Project Planning Group, email id -